For high voltage input/output (I/O) and system-on-chip (SoC) applications, various Drain extended MOS (DeMOS) devices have been proposed in the past decades. These devices can be used in a wide range of applications like radio frequency power amplifiers, line drivers for interfaces, USB, and buck converters. But these devices are prone to failure under high voltage/current and electrostatic discharge (ESD) conditions. The physical mechanism behind the failure is currently under investigation in the ESD community. Furthermore, the lack of detailed physical understanding towards the failure mechanisms results in a major roadblock for the development of analytical models for these devices and eventually the computer aided design (CAD) tools, which can help in the design and electronic security device (ESD) failure analysis of ultra large scale integrated (ULSI) circuits and systems.

Mayank Shrivastava has provided a clear physical insight into the ESD failure mechanism of drain extended devices, which is further used for engineering the existing DeMOS devices. The modified DeMOS devices were found to be highly reliable under the ESD conditions in addition to exhibiting an excellent mixed signal performance. Previously different device options were used for high voltage applications like the thick gate-oxide devices to increase the breakdown voltage or non-silicon devices for radio frequency applications.

Using the invented and engineered DeMOS devices, integration of high voltage and high frequency applications are possible in standard complementary metal oxide semiconductor (CMOS). This will greatly reduce the overall cost of various products. "Furthermore, the detailed physical understanding of the device operation and the failure will help in developing analytical models or eventually will help in designing CAD tools for design and ESD failure analysis of I/O circuit blocks, which is still a desperate need in the semiconductor industry for its pre-silicon phase of development," explains V. Ramgopal Rao, professor, Department of Electrical Engineering, IIT Bombay. This work was published in various international conferences/journals and resulted in multiple patents, which was found to be useful by the semiconductor industry in the design of highly efficient system on chip.

"By in-depth device simulation studies, Mayank has now developed models which allow a deeper nsight into the behavior of current filaments in devices operated at extreme voltages, currents and temperatures," adds Harald Gossner, senior principal, Overvoltage Robust Design, Infineon Technologies, Munich.