“Remarkable” is how Stanford University professor Cal Quate describes his onetime PhD student Kathryn Guarini. In the mid- 1990’s, Guarini and Quate developed a lithography technique that let engineers pattern integrated-circuit features smaller than 100 nonometers, which packed more circuits, and thus more power, onto chips. Since 1999, when she joined IBM Research, Guarini has led Big Blue’s development of three-dimensional circuits- a semiconductor frontier. For decades, designers have made transistors smaller but have continued to place them side by side in a single layer. Guarini’s techniques can stack transistors in two or three layers, vastly increasing the number that fit on a chip. She has also shortened the metallic connections between transistors, accelerating processing speeds. Challenges remain, including how to limit the heat a 3-D chip produces. But colleagues predict Guarini will prevail. Says fellow IBM researcher Philip Wong, “Whatever she touches, she turns to gold.”